module ram_2p_32d_192w_wrapper(
    input                   clk ,
    input   [9:0]           ram_2p_cfg_register ,

    input                   wren_n ,
    input   [4:0]           waddr ,
    input   [191:0]         wdata ,
    input                   rden_n ,
    input   [4:0]           raddr ,
    output  [191:0]         rdata
) ;

    wire    [95:0]          rdata_1, rdata_2 ;
    wire    [95:0]          wdata_1, wdata_2 ;
    assign wdata_1 = wdata[191:96] ;
    assign wdata_2 = wdata[95:0] ;
    assign rdata = {rdata_1, rdata_2} ;

    ram_2p_d32_w96 U1_ram_2p_32d_96w ( 
        .QA(rdata_1), 
        .CLK(clk), 
        .CENA(rden_n),//read enable,active low 
        .CENB(wren_n),//write enable,active low
        .AA(raddr), 
        .AB(waddr), 
        .DB(wdata_1), 

        .STOV(ram_2p_cfg_register[9]), 
        .STOVAB(ram_2p_cfg_register[8]), 
        .EMA(ram_2p_cfg_register[7:5]), 
        .EMAW(ram_2p_cfg_register[4:3]),
        .EMAS(ram_2p_cfg_register[2]), 
        .EMAP(ram_2p_cfg_register[1]), 
        .RET1N(ram_2p_cfg_register[0])
    );

    ram_2p_d32_w96 U2_ram_2p_32d_96w ( 
        .QA(rdata_2), 
        .CLK(clk), 
        .CENA(rden_n),//read enable,active low 
        .CENB(wren_n),//write enable,active low
        .AA(raddr), 
        .AB(waddr), 
        .DB(wdata_2), 

        .STOV(ram_2p_cfg_register[9]), 
        .STOVAB(ram_2p_cfg_register[8]), 
        .EMA(ram_2p_cfg_register[7:5]), 
        .EMAW(ram_2p_cfg_register[4:3]),
        .EMAS(ram_2p_cfg_register[2]), 
        .EMAP(ram_2p_cfg_register[1]), 
        .RET1N(ram_2p_cfg_register[0])
    );

endmodule
